Design for Testability in Timely Testing of Vlsi Circuits

Even though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system.Two main issues related to test and security domain are scan-based attacks and misuse of JTAG interface. Design for testability presents effective and timely testing of VLSI circuits. The project is to test the circuits after design and then reduce the area, power, delay and security of misuse. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in selftest (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both. BIST is usually performed using pseudorandom pattern generators (PRPGs). Among the advantages of pseudorandom BIST are: (1) the low cost compared to testing from automatic test equipment (ATE). (2) The speed of the test, which is much faster than when it is applied from ATE. (3) The applicability of the test while the circuit is in the field, and (4) the potential for high quality of test. Keyword: Testing, scan-based attacks, misuse of JTAG interface, BIST.